1. Field of the Invention
The present invention relates to a semiconductor device which has an internal voltage reduction circuit for providing an internal voltage by reducing an external voltage.
2. Description of the Related Art
Recently, the degree of integration of semiconductor integrated circuits has increased. MOS transistors have become smaller in order to provide many functions in one chip.
The accuracy of processing machines has also improved, and therefore the size of MOS transistors can be easily reduced.
However, as the MOS transistors become smaller, a source voltage for circuits which comprise semiconductor integrated circuits, that is, the voltage of an external power source supplied to the internal circuit of the semiconductor integrated circuit, may be more likely to deteriorate the internal MOS transistors.
Although the size of the MOS transistor is being reduced, the operating voltage of the MOS transistors has not changed (it has is not been reduced). Therefore, the voltage can exceed the withstand voltage of the MOS transistors, reducing the reliability.
The operating voltage of the MOS transistor is set according to standards (or working conditions) independently from the reduced size of the MOS transistors. Since the size of MOS transistors is being reduced, the standards for semiconductor integrated circuits using the MOS transistors should be revised. However, the operating voltage according to the standards have not been reduced.
Therefore, as shown in FIG. 9, an internal voltage reduction circuit 100 provided in the semiconductor integrated circuit reduces the voltage VEX (for example, 3.3 V) from an external power source to an internal voltage VINT (for example, 2.0 V) which meets the withstand voltage of the reduced MOS transistors, and supplies the internal voltage to the internal circuit 101.
Thus, the electric power consumption can be reduced in the operation of the semiconductor integrated circuit.
However, the input circuit 102 and the output circuit 103 must be capable of withstanding the voltage VEX from the external power source.
That is, in a p-channel MOS transistor 104 in the input circuit 102, when the voltage of an input signal IN is at the H level, the withstand voltage between a drain with a substrate and a gate is exceeded. When the voltage of the input signal IN is at the L level, the withstand voltage between a source and the gate is exceeded.
In an n-channel MOS transistor in the input circuit 102, when the voltage of the input signal IN is at the H level, the withstand voltage between the source and the gate is exceeded, and when the voltage of the input signal IN is at the L level, the withstand voltage between the drain with a substrate and the gate is exceeded.
Similarly, in a p-channel MOS transistor 106 in the output circuit 103, when a signal INO is at the H level, the withstand voltage between the source and the gate is exceeded, and when the signal INO is at the L level, the withstand voltage between the drain with a substrate and the gate is exceeded.
In an n-channel MOS transistor 107 in the input circuit 103, when the signal INO is at the H level, the withstand voltage between a source and a gate is exceeded, and when the signal INO is at the L level, the withstand voltage between a drain with a substrate and a gate is exceeded. The voltage of the signal INO at the H level is changed from the internal voltage VINT to the external voltage VEX by a level shift circuit 108.
Thus, the input circuit 102 and the output circuit 103 must be capable of the voltage VEX of the external power source to send and receive signals to and from an external circuit.
Therefore, for the MOS transistor to have a gate which withstands the voltage VEX of the external power source, the oxide film of the gate of the MOS transistor must have a thickness which allows it to withstand the voltage VEX of the external power source.
According to the above structure, the semiconductor integrated circuit has input circuit 102 and output circuit 103 with gates which can withstand the voltage of the external power source.
However, the process for manufacturing the semiconductor integrated circuit must produce two kinds of MOS transistors. One of the MOS transistors has a thin gate oxide film (with a thickness of 4 nm), while the other MOS transistor has a thick gate oxide film (with a thickness of 9 nm).
Because two kinds of gate oxide films with different thicknesses must be produced, at least four extra steps are required as compared with the normal manufacturing process for producing gate oxide films with the same thickness. Therefore, the manufacturing costs are increased, and the price of the produced chip is also disadvantageously increased.
To solve this problem, a circuit structure in which the gate oxide films in the MOS transistors which constitute the input circuit and the output circuit and the gate oxide films in the MOS transistors which constitute the internal circuit have the same thickness has been proposed.
In the input circuit shown in FIG. 10, the voltage reduction circuit 115 reduces the external voltage VEX to the internal voltage VINT, and supplies the voltage VINT to the internal circuit. When the voltage of the input signal IN is at the L level, the voltage of a source and a gate of a p-channel MOS transistor 110 is within the withstand voltage. Thus, the withstand voltage is satisfied.
Because a p-channel transistor 112 whose gate is connected to ground is inserted between a MOS transistor 110 and an n-channel MOS transistor 113, the voltage at the drain of the MOS transistor 110 is reduced. When the voltage of the input signal IN is at the H level, the voltage between the drain and the gate of the MOS transistor 110 is within the withstand voltage. Thus, the withstand voltage is satisfied.
The phrase xe2x80x9cthe voltage is within the withstand voltage (satisfy the withstand voltage)xe2x80x9d means that a voltage less than the withstand voltage of the gate oxide film of the MOS transistor is applied between a gate and a source (or a drain).
Similarly, an n-channel MOS transistor 114 is inserted between a gate of an n-channel MOS transistor 113 and an input terminal 116 (which is connected to an external pad).
When the input signal IN is at the H level, the voltage of the signal at the H level (the voltage VEX of the external power source) applied to the gate of the MOS transistor 113 is reduced to VEXxe2x88x92VTN by a threshold voltage VTN of a MOS transistor 114 so that the voltage between the gate and the source of the MOS transistor 113 is within the withstand voltage.
When the input signal IN is at the L level, the voltage of the signal at the L level (the ground level) applied to the gate of the MOS transistor 113 is increased to VTP by the threshold voltage VTP of the MOS transistor 114, and the voltage applied to the drain is changed to the internal voltage VINT by a voltage reduction circuit 115. Thus, the withstand voltage of the gate and the drain of the MOS transistor 113 is satisfied.
In the output circuit shown in FIG. 11, a p-channel MOS transistor 120, a p-channel MOS transistor 121, an n-channel transistor 122, and an n-channel MOS transistor 123 are connected in series.
The source of the MOS transistor 120 is connected to a terminal at an external voltage VEX. The signal SB output from the level shifter 125 is input to the gate of the MOS transistor 120. The drain of the MOS transistor 120 is connected to a source of the MOS transistor 121.
The control signal SP at a voltage VSP is continuously input from the reference power source 126 to the gate of the MOS transistor 121. the control signal SN at a voltage VSN is continuously input from the reference power source 126 to the gate of the MOS transistor 122.
When the MOS transistor 120 is turned on, the voltage VSP of the control signal SP sets the voltage between the gate and the source (or the drain) of the MOS transistor 121 to less than the withstand voltage of the gate oxide film, and turns on the MOS transistor 121.
Similarly, when the MOS transistor 123 is turned off, the voltage VSN of the control signal SN sets the voltage between the gate and the source (or the drain) of the MOS transistor 122 to less than the withstand voltage of the gate oxide film, and turns on the MOS transistor 122.
A signal SB which has been changed from the voltage of the signal SA by the level shifter 125 is input to the gate of the MOS transistor 120. The level shifter 125 has changed the signal SA at the H level which is the internal voltage VINT from the internal circuit to the voltage VEX at the H level, and has changed the signal SA at the L level which is the ground voltage from the internal circuit to the voltage VL at the L level.
The voltage VL sets the voltage between the gate and the drain (or the source) of the MOS transistor 120 to less than the withstand voltage of the gate oxide film, and is a voltage for turning on the MOS transistor 120.
When the signal SA at the H level is input while the MOS transistors 121 and 122 are in the ON-state, the signal SB is increased to the H level so that the MOS transistor 120 is turned off, the signal SA is changed to the H level which is the internal voltage VINT so that the MOS transistor 123 is turned on, and the output circuit outputs an output signal OUT at the L level which is the ground level.
When the signal SA at the L level is input while the MOS transistors 121 and 122 are in the ON-state, the signal SB is changed to the voltage VL so that the MOS transistor 120 is turned on, the signal SA is changed to the L level so that the MOS transistor 123 is turned off, and the output circuit outputs the output signal OUT at the H level which is the external voltage VEX.
In the above-mentioned input circuit, the MOS transistor 114 for reducing the voltage VEX of the externally input signal IN is inserted between the gate of the MOS transistor 113 and the input terminal 116. Therefore, the rising and lowering of the signal applied to the gate of the MOS transistor 113 are slow, and the voltage applied to the gate of the MOS transistor 113 is lowered to VINTxe2x88x92VTN by the threshold voltage of the MOS transistor 114, delaying the supply of the signal INS to the internal circuit. Thus, there is the problem in that the operating speed of the semiconductor integrated circuit is decreased.
That is, the rising of the input signal IN from the L level to the H level, and the lowering of the input signal IN from the H level to the L level which are the variations of the signal level input to the gate of the MOS transistor 113 are delayed by a time constant determined by the resistance component of the MOS transistor 114 and the gate capacity of the MOS transistor 113.
In the above-mentioned output circuit, when the voltage level of the output signal OUT is changed from the L level to the H level, the voltages at the drain and the source of the MOS transistor 121 are suddenly increased. Then, because of the parasitic capacitance of the gate and the source of the MOS transistor 121, as the voltages at the drain and the source are increased, the voltage VSP of the control signal SP is increased, the MOS transistor 121 is turned off, and therefore the rise of the output signal OUT from the L level to the H level is disadvantageously delayed.
The parasitic capacitance of the gate and source includes a capacitance component of the overlapping section of the source electrode and the gate electrode of the MOS transistor, and a capacitance component between the sides of the source electrode and the gate electrode.
Further, in the above-mentioned output circuit, when the voltage level of the output signal OUT is changed from the H level to the L level, the voltage at the drain of the MOS transistor 122 is reduced. Then, because of the parasitic capacitance of the gate and the drain of the MOS transistor 122, as the voltage VSN of the control signal SN is decreased, the MOS transistor 122 is turned off, and therefore the rise of the output signal OUT from the H level to the L level is disadvantageously delayed.
To prevent the variations of the voltages VSP and VSN in the above-mentioned output circuit, the performance for driving the control signals SP and SN in the reference power source may be increased. However, this method significantly increases the electric power consumption of the reference power source 126.
It is therefore an object of the present invention to provide a semiconductor device which does not increase the number of steps in the manufacturing process, which eliminates delays in the input and output signals, and which improves the reliability of the input circuit and the output circuit.
In the first aspect of the present invention, the output circuit which produces an external signal at a first voltage from an internal signal at a reduced second voltage and which outputs the external signal from an output terminal, comprises; first and second MOS transistors having drains connected to the output terminal, and having gates connected to a control signal line; a third MOS transistor having a source connected to a power source of the first voltage, and having a drain is connected to a source of the first MOS transistor; a fourth MOS transistor having a source is connected to a ground, having a drain connected to a source of the second MOS transistor, and of which gate is connected to an internal signal line; a voltage changer, which changes the voltage of the internal signal, connected to the gate of the third MOS transistor; a first capacitor connected between a gate of the first MOS transistor and a gate of the third MOS transistor; and a second capacitor connected between a gate of the second MOS transistor and a gate of the fourth MOS transistor.
In the second aspect of the present invention, the first, second, third, and fourth MOS transistors, the voltage changer, the first and second capacitor are formed in a semiconductor integrated circuit.
In the third aspect of the present invention, a capacitance of the first capacitor is the same as a parasitic capacitance between the gate and the drain of the first MOS transistor, and a capacitance of the second capacitor is the same as a parasitic capacitance between the gate and the drain of the second MOS transistor.
In the fourth aspect of the present invention, the voltage changer outputs the control signal at the first voltage when the internal signal is at the ground voltage, and outputs the control signal at a voltage less than a withstand voltage of a gate oxide film when the internal signal at the second voltage.
In the fifth aspect of the present invention, the output circuit which produces an external signal at a first voltage from an internal signal at a reduced second voltage and which outputs the external signal from an output terminal, comprises: first and second MOS transistors having drains connected to the output terminal, and having gates connected to a control signal line; a third MOS transistor having a source connected to a power source of the first voltage, and having a drain connected to a source of the first MOS transistor; a fourth MOS transistor having a source is connected to a ground, having a drain connected to a source of the second MOS transistor, and having a gate connected to an internal signal line; a voltage changer, which changes the voltage of the internal signal, connected to the gate of the third MOS transistor; a first diode connected between a gate of the first MOS transistor and a gate of the third MOS transistor; and a second diode connected between a gate of the second MOS transistor and a gate of the fourth MOS transistor.
In the sixth aspect of the present invention, the first, second, third, and fourth MOS transistors, the voltage changer, the first and second diodes are formed in a semiconductor integrated circuit.
In the seventh aspect of the present invention, the number of the first diodes connected in series is adjusted depending on a difference in voltage between the gate of the third transistor and the gate of the first transistor, and the number of the second diodes connected in series is adjusted depending on a difference in voltage between the gate of the second transistor and the gate of the third transistor.
In the eighth aspect of the present invention, the voltage changer outputs the control signal at the first voltage when the internal signal is at the ground voltage, and outputs the control signal at a voltage less than a withstand voltage of a gate oxide film when the internal signal at the second voltage.
In the ninth aspect of the present invention, the input circuit which produces an internal signal at a reduced second voltage from an external signal at a first voltage and which inputs the internal signal to an input terminal, comprises: a first MOS transistor having a source connected to a first terminal at the second voltage, and having a gate connected to the input terminal, a second MOS transistor having a source connected to a drain of the first MOS transistor, and having a gate connected to a ground; a third MOS transistor having a drain connected to a drain of the second MOS transistor, and having a source connected to the ground; a fourth MOS transistor having a source connected to a gate of the third MOS transistor, having a gate connected to a line at the second voltage, and having a drain connected to the input terminal; and a capacitor connected between a gate of the third MOS transistor and the input terminal.
In the tenth aspect of the present invention, the first, second, third, and fourth MOS transistors, and the capacitor are formed in a semiconductor integrated circuit.
In the eleventh aspect of the present invention, the input circuit further comprises a diode connected between the gate of the third MOS transistor and the input terminal in parallel to the capacitor.
In the twelfth aspect of the present invention, the input circuit further comprises a diode connected between a power source of the first voltage and the first terminal.
In the thirteenth aspect of the present invention, a capacitance of the capacitor is set so that a voltage between the gate and the source, or the drain, of the third MOS transistor does not exceed a withstand voltage of a gate oxide film when the input terminal is increased to the first voltage.
According to the output circuit of the present invention, the first and second capacitors transmit the variations of the control signal and the internal signal to the gates of the first and second MOS transistors. Therefore, variations (increases or decreases) of the voltages of the gates of the first and second MOS transistors can be prevented. Thus, the operation of the first and second MOS transistors is stabilized, the delay between a change in the internal signal and a change in the external signal is shortened, and the operating speed can be increased.
According to the input circuit of the present invention, the capacitor allows the voltage at the gate of the third MOS transistor (23) to follow the change of the voltage of the input signal. The switching ON or OFF of the third MOS transistor can be performed at a high speed. Thus, the delay between a change in the internal signal and a change in the external signal is shortened, and the operating speed can be increased.
As a result, the number of steps in the manufacturing process can be reduced (four steps can be eliminated) as compared with the process for manufacturing the conventional integrated circuit with MOS transistors with different thicknesses of the input circuit and the output circuit. Therefore, the production time can be shortened, the manufacturing costs can be reduced, and the prices of the chips can be reduced.